1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having an error correcting code (ECC) circuit.
2. Description of the Related Art
With the advance in micropatterning technique and the decrease in operating voltage of semiconductor memory devices, soft errors in, e.g., static random access memories (SRAMs) have come to pose a problem. The known soft errors are classified into those caused by α-rays emitted from a radioactive substance contained in the materials such as solder used for the semiconductor devices and those caused by fast neutrons arriving as cosmic rays.
An effective measure against soft errors is to mount an ECC circuit in a semiconductor memory device. The ECC circuit can effectively relieve not only the soft errors but also hard errors which occur due to physical failures. The ECC circuit often employs, e.g., a single error correction—double error detection (SEC-DED) system capable of correcting a 1-bit error and detecting a 2-bit error.
In the semiconductor memory device, a memory cell corresponding to a designated address is selected by a row selection circuit and column selection circuit. N-bit data (word) read out from simultaneously selected memory cells is input to the ECC circuit, error-corrected, and output from the semiconductor memory device. The SEC-DED scheme can correct a 1-bit error in the N-bit data. However, an error of 2 or more bits cannot be corrected.
The physical positions of memory cells which store the data of word (N bits) to be simultaneously read out are determined by the arrangements of the row selection circuit and column selection circuit. Normally, the memory cells are regularly arrayed.
As the elements are micropatterned by scaling, and the voltage is decreased, the number of margin-based hard errors caused by the parasitic effect or element variation in the chip is increasing in addition to those which are caused by random reasons such as a crystal defect and dust. The rate of such margin-based hard errors is not uniform and changes depending on the memory cell position.
For this reason, if the fraction defective of memory cells arranged at the edge of the memory cell array is higher than that for memory cells arranged at other positions, the memory cells with the high fraction defective are simultaneously read-accessed. Hence, the rate of errors of 2 or more bits is considerably higher in this word than in other words. As a result, the relief rate by ECC in the whole memory becomes low.
As a related technique of this kind, a technique of reducing the coupling capacitance between word lines is disclosed (U.S. Pat. No. 5,097,441).